SQ 5 Losing Sync with DX-32

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This topic contains 6 replies, has 6 voices, and was last updated by Profile photo of KeithJ A&H KeithJ A&H 1 month, 1 week ago.

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    Profile photo of Mac

    I’ve had this happen a few times now and a simple unplug and replug of the ethercon instantly fixes it. Makes me nervous that this is going to happen during show. Just Upgraded to latest Firmware today so haven’t been able to test. Any thoughts?

    Profile photo of ddff_lv

    Let’s hope v1.3 comes with support for DX32. Until then DX168 is the way.

    Profile photo of Alex A&H
    Alex A&H

    Hi Mac,

    The DX32 is not currently supported on SQ.

    This is planned and will be added as soon as possible.



    Profile photo of Zero

    Hi Alex,

    Do we anticipate DX32 support in v1.3? If so, would the recently announced Prime I/O that works with DX32 be supported potentially at that time? Along those same lines, are there A/D-D/A specs for Prime I/O available? This seems like it would be a great solution for the studio environment!


    Profile photo of KeithJ A&H
    KeithJ A&H

    Hi Zero,

    Yes, DX32 support is planned for V1.3, and then you could absolutely use a setup which includes SQ+DX32+Prime!
    As you correctly point out this would be a fantastic setup for a studio, especially with the support for the DAW Control Driver coming soon to SQ.


    Profile photo of Steffen R
    Steffen R

    and when can we expect 1.3?

    Are there any plans on updating the older stageboxes (AB, AR) to 96kHz and AES outputs?

    a 32 Input, 16 Output solution with some AES in and Out would be great for most applications

    Profile photo of KeithJ A&H
    KeithJ A&H

    Hi Steffen,

    We aim to release SQ V1.3 towards the end of Q3.
    Suggestions for more 96kHz expanders noted – we have had quite a few requests for larger units actually, so I wouldn’t rule it out, but in the meantime, 2x DX168’s rackmounted and cascaded would give you this channel count. The DX protocol is 32×32 channels, so any more than this, i.e. extra AES would necessitate the jump to GigaACE (128×128).


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