Reply To: Monitor outputs dropped mid show

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#37461
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Mark McFarlane
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Some FPGAs always need to have the code/configuration reloaded on power up (not necessarily the same thing is reboot). I suspect there are some FPGA designs that can persist their code when power is down, or have the code in local flash or static memory from which they load the ‘last configuration’ from.

Changing show files seems like a sure fire way to reprogram the FPGA, and that is faster than rebooting. Maybe the workaround is to save a she, reload a default show, then reload your saved show. That’s only a few seconds and could be performed between songs.

I don’t know what chip the GLD has or I could research it more. First time I open it up I’ll check :).

I’ll ask in my support ticket.